Interconnection and packaging related issues are among the main factors that determine not only the number of circuits that can be integrated on a chip, but also the performance of the chip. These issues have gained in importance as advances in chip design have led to reduced feature sizes of transistors and enlarged die sizes. Industry has come to realize that merely having a fast chip will not result in a fast system; it must also be supported by equally fast and reliable packaging.
Essentially, packaging supplies the chip with signals and power, and performs other functions such as heat removal, physical support and protection from the environment. Another important function is simply to redistribute the tightly packed I/Os off the chip to the I/Os of a printed wiring board.
An example of a package-chip system is the "flip-chip" integrated circuit mounted on an area array organic package. Flip-chip mounting entails placing solder bumps on a die or chip, flipping the chip over, aligning the chip with the contact pads on a substrate, and reflowing the solder balls in an oven to establish bonding between the chip and the substrate. This method is advantageous in certain applications because the contact pads are distributed over the entire chip surface rather than being confined to the periphery, as in wire bonding and most tape-automated bonding (TAB) techniques. As a result, the maximum number of I/O and power/ground terminals available can be increased, and signal and power/ground interconnections can be more efficiently routed on the chips.
However, with existing flip-chip packaging techniques, thermal expansions due to mismatches between the semiconductor chip and the substrate can cause strains at the bumps, and thus, could lead to failure. Regardless of which packaging technique is employed, material issues such as the aforementioned thermally induced strain causes a chip package designer to select and match materials with great care.
In the manufacture of integrated circuit packaging, the chip package designer attempts to obtain ever greater wiring densities while at the same time forming interconnections between adjacent layers that provide reliable circuits with as little inductance and resistance as possible. Thus, the formation of high quality via holes, or vias, that are used for interconnections, is an important aspect of forming high quality interconnections.
It has been known to use lasers to form vias in multi-layered laminated substrates. Laser pulses are applied to drill through the substrate as desired. Each laser pulse applied has an energy density that is greater than an ablation threshold of the material and removes a small amount of material. A large number of pulses are applied until the necessary material has been removed. In a typical via drilling application, pulses are applied at a repetition rate of 2,000 to 10,000 per second, for a short burst of less than one second in duration. The beam is then turned off and moved to the location of the next via to be formed, where another short burst of pulses is applied.
Increasing the pulse repetition rate of a laser typically decreases the energy density of each output pulse. If the pulse repetition rate is increased too much, the pulse energy density will fall below the ablation threshold. This effect produces an effective maximum pulse rate at which a particular laser may be used for via formation. Increasing the pulse repetition rate during via formation, while maintaining an energy density sufficient to exceed the ablation threshold would allow the time necessary to form each via to be decreased. This would lead to a decrease in the cost of manufacturing electrical component packages. On the other hand, in order to form consistent, high-quality vias, it is important that the applied energy be consistent from pulse to pulse. A need arises for a laser via drilling system that operates at an increased pulse repetition rate, but provides output pulses of sufficient energy and consistent pulse to pulse energy.